1. Field of the Invention
The present invention relates to an address generator which can be used to supply sound data to a digital filter used in sound processings of ADPCM,.ATRAC, PACS, MREGI, II, etc.
2. Description of the Related Art
Filter processing using a finite impulse response (FIR) filter, etc. is performed in processing of a digital sound. A digital signal processor (DSP) supplies sound data from a memory to this digital filter.
The digital signal processor (DSP) is set to execute many processings in a limited instruction field. Therefore, a horizontal coding system for executing one or more commands at a high speed by one instruction is used. The horizontal coding system is a method for describing one or more commands by one instruction field. In contrast to this horizontal coding system, there is a vertical coding system used in a complex instruction set computer (CISC). This vertical coding system is a method for describing one command by using a plurality of instructions.
In the vertical coding system, it is possible to use a direct address for directly describing an address value in addressing of a memory. However, a width of the instruction field is determined in the horizontal coding system so that no address value can be directly designated. When the address value of a memory is stored to a register in advance and the memory is accessed, indirect addressing for designating a register value indicative of the stored address is used.
For example, when a memory having 64 k bits is accessed, address values of 16 bits must be allocated into instructions in the case of direct addresses. In contrast to this, in the case of the indirect addressing, eight registers of 16 bits are prepared and addresses are stored into these registers. An address required for a memory accessing operation is take out of a register by designating this register. In this indirect addressing, only three address designating bits are required for instructions. Thus, an allocating amount of the memory addressing of the instruction field is reduced as much as possible in the digital signal processor (DSP) using the horizontal coding system.
In the case of the register indirect addressing, an address value within a register must be updated after the indirect addressing is performed. As a technique often used at this time, there is a post incremental technique in which the address value within the register is incremented by +1 after the addressing. There is also a post decremental technique in which the address value within the register is decremented by -1 after the addressing. Further, there is a post incremental or decremental technique with an offset value in which a certain constant value is added or subtracted from the address value within the register. In the case of the post incremental technique or the post decremental technique, an incremental or decremental value is determined so that it is not necessary to designate an offset value. In contrast to this, in the case of the post incremental or decremental technique with an offset value (as addressing with an offset value), the offset value must be provided by instructions.
The same bit allocation as an address is also required for the offset value so that no offset value can be directly designated in the horizontal coding system. Therefore, it is considered to use a method in which this offset value is also stored to the register and is designated by indirect designation of the register. However, a using frequency of such addressing with the offset value is low. Therefore, no bits are normally allocated to the offset addressing as much as possible.
FIG. 1 is a circuit diagram showing one example of an address generator in a general digital signal processor (DSP). In this address generator, an offset register is fixedly arranged and the same register value is used as an offset value at any time when addressing with an offset is performed. Namely, as shown in FIG. 1, this circuit has eight auxiliary registers AR0 to AR7 and one register such as AR0 among these auxiliary registers is used as an offset register. When the addressing with an offset is performed, a value of the register AR0 is used at any time.
FIG. 2 is a circuit diagram showing another example of the address generator in the general digital signal processor (DSP). In this address generator, one offset register is allocated to one address register so that offset register designation is omitted. Namely, as shown in FIG. 2, this circuit has eight address registers R0 to R7, eight offset registers N0 to N7 and eight modulo registers M0 to M7. One offset register and one modulo register are allocated to each of the address registers. Accordingly, when one address register is selected, the offset register and the modulo register corresponding to this address register are automatically selected and used in addressing.
The digital signal processor (DSP) has many applications for repeatedly accessing a certain memory region within a memory. For example, modulo addressing is used as one of these applications. In this modulo addressing, when a filter calculation is made by using sound data stored to the memory, starting and ending addresses in the memory region are provided to a register. When an updated address value is greater than the ending address, the next address is returned to the starting address so that the addressing is repeatedly performed within the same memory region.
The starting and ending addresses as modulo values are normally designated by indirect designation of a register. In the general digital signal processor (DSP), one modulo register is fixedly provided to save an instruction field and a value of this modulo register is used at any time at a modulo addressing time.
In the address generator shown in FIG. 2, when one address register is selected, a modulo register corresponding to this address register is automatically selected and used in addressing.
However, a value of the register AR0 is used at any time in a general structure of the address generator shown in FIG. 1 when the addressing with an offset is performed. Accordingly, only one offset value can be set in this general structure. In a general structure of the address generator shown in FIG. 2, an offset register and a modulo register correspond to each of the eight address registers. Accordingly, a degree of freedom of the addressing is increased, but the number of offset registers and modulo registers is increased as the number of address registers is increased. Therefore, a hardware scale of this address generator is increased.
Further, in a structure for fixedly providing one modulo register in the modulo addressing, a degree of freedom of the modulo addressing is reduced. On the other hand, hardware of the general structure of the address generator shown in FIG. 2 is increased in size.